Embodiments of the present invention relate to computer systems and more particularly to methods and apparatus for testing and validating such systems.
To save on the number of pins and traces needed to support the bandwidth of ever-faster semiconductor devices such as microprocessors and so forth, the data rates on the busses that connect such devices to memory, graphics and peripherals must constantly scale to higher rates. Interactions between such devices are observed for purposes of logic validation, in order to debug the devices and ship product. For modern computer systems including their semiconductor devices and busses, validation systems/tools incorporating logic/traffic trace probes are used to debug and validate new systems and boards for shipment, and also to quickly diagnose field return issues that may be design or process related or both in order to avoid costly product recalls.
A logic probe for obtaining data should add virtually no cost to the product under test, and thus it should be attachable within the space, thermal, and other product constraints of the original product. It should be easy to set up, operate with acceptable error rates, and be able to work reliably/robustly over manufacturing variations. Point-to-point or other high-speed links have very small signaling margins, and thus a probe should not perturb the bus significantly. For example, in some systems a 15% voltage and 5% timing eye margin reduction may be the maximum allowed, and less is better. The output of the logic probe should be of acceptable recovered trace integrity (i.e., within a couple orders of magnitude as reliable as the worst case for the link itself in terms of bit error rate (BER) performance). Finally, the probe should not change either the static latency or dynamic timing of the link significantly and therefore should not introduce any significant timing delay or delay variation when inserted.
Current probing methods include direct tap resistive probes. However, direct tap probes generally do not scale to higher bandwidth present in today's systems. Thus, other methods of probing such as mirrored (i.e., duplicate) ports directly on the device, regenerative repeaters (with built-in mirrored ports) and electromagnetic coupler-based probes are being developed for future generation systems.
However, each of these alternatives suffers from drawbacks. Mirroring ports on a semiconductor device introduces unacceptable product cost adders because of the silicon area impact, and the cost and complexity of added routing and pads and pins/balls on the die and package. Inserting regenerating repeaters at the beginning or end of a channel lengthens the inter-device channel, resulting in some eye margin reduction. Such repeater probes also add appreciable latency to a link and can mask bugs or otherwise alter system behavior. Probing with interposer couplers, both mid-bus and socketed interposers, degrades overall channel performance and introduces route-ability and design challenges to fit sufficiently large/powerful electromagnetic couplers into the pin fields and bus pitches. Also, space and thermal constraints often limit the number of links that may be probed in one socket using electromagnetic couplers, resistor taps or optical modulator-based probes.
Ultimately, the purpose of a logic probe is to monitor the bus traffic to help determine the state of the device over time and to find errors inside the device by combining the state information with software simulation or hardware emulation. To reliably debug the insides of such a device, a link being probed should have an acceptably low BER, both for the link being observed and for the captured trace. Bit errors on the bus will imply false state information and complicate debug. Second, the timing of traffic on an interconnect should not be perturbed. Current testing systems suffer from drawbacks of expense in terms of real estate and also can cause perturbation on a link, and can suffer from a high BER due to the speed of the link.